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<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">I2C Callback Events<div class="ingroups"><a class="el" href="group__group__scb.html">SCB          (Serial Communication Block)</a> &raquo; <a class="el" href="group__group__scb__i2c.html">I2C (SCB)</a> &raquo; <a class="el" href="group__group__scb__i2c__macros.html">Macros</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>Macros to check I2C events passed by <a class="el" href="group__group__scb__i2c__data__structures.html#ga5d6df20d77d2690048aaef8fe9e57e2e">cy_cb_scb_i2c_handle_events_t</a> callback. </p>
<p>Each event is encoded in a separate bit, and therefore it is possible to notify about multiple events. </p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gab1b3af0c61cd17e209d3c95aedd89f7b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__i2c__macros__callback__events.html#gab1b3af0c61cd17e209d3c95aedd89f7b">CY_SCB_I2C_SLAVE_READ_EVENT</a>&#160;&#160;&#160;(0x00000001UL)</td></tr>
<tr class="memdesc:gab1b3af0c61cd17e209d3c95aedd89f7b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates that the slave was addressed and the master wants to read data.  <a href="#gab1b3af0c61cd17e209d3c95aedd89f7b">More...</a><br /></td></tr>
<tr class="separator:gab1b3af0c61cd17e209d3c95aedd89f7b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacbc6de23c9ce6b3b01746244e27c8bed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__i2c__macros__callback__events.html#gacbc6de23c9ce6b3b01746244e27c8bed">CY_SCB_I2C_SLAVE_WRITE_EVENT</a>&#160;&#160;&#160;(0x00000002UL)</td></tr>
<tr class="memdesc:gacbc6de23c9ce6b3b01746244e27c8bed"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates that the slave was addressed and the master wants to write data.  <a href="#gacbc6de23c9ce6b3b01746244e27c8bed">More...</a><br /></td></tr>
<tr class="separator:gacbc6de23c9ce6b3b01746244e27c8bed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabe3e8539e5a47b1a419cd07a5aa1531e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__i2c__macros__callback__events.html#gabe3e8539e5a47b1a419cd07a5aa1531e">CY_SCB_I2C_SLAVE_RD_IN_FIFO_EVENT</a>&#160;&#160;&#160;(0x00000004UL)</td></tr>
<tr class="memdesc:gabe3e8539e5a47b1a419cd07a5aa1531e"><td class="mdescLeft">&#160;</td><td class="mdescRight">All slave data from the configured Read buffer has been loaded into the TX FIFO.  <a href="#gabe3e8539e5a47b1a419cd07a5aa1531e">More...</a><br /></td></tr>
<tr class="separator:gabe3e8539e5a47b1a419cd07a5aa1531e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gada6c481df3423c3c0d7db05fd626534a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__i2c__macros__callback__events.html#gada6c481df3423c3c0d7db05fd626534a">CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT</a>&#160;&#160;&#160;(0x00000008UL)</td></tr>
<tr class="memdesc:gada6c481df3423c3c0d7db05fd626534a"><td class="mdescLeft">&#160;</td><td class="mdescRight">The master has read all data out of the configured Read buffer.  <a href="#gada6c481df3423c3c0d7db05fd626534a">More...</a><br /></td></tr>
<tr class="separator:gada6c481df3423c3c0d7db05fd626534a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae44345d38014821cc5d5c918dd074324"><td class="memItemLeft" align="right" valign="top"><a id="gae44345d38014821cc5d5c918dd074324"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__i2c__macros__callback__events.html#gae44345d38014821cc5d5c918dd074324">CY_SCB_I2C_SLAVE_RD_CMPLT_EVENT</a>&#160;&#160;&#160;(0x00000010UL)</td></tr>
<tr class="memdesc:gae44345d38014821cc5d5c918dd074324"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates the master completed reading from the slave (set by the master NAK or Stop) <br /></td></tr>
<tr class="separator:gae44345d38014821cc5d5c918dd074324"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa509ff3cd20d1b1d31e3c22e7c28871f"><td class="memItemLeft" align="right" valign="top"><a id="gaa509ff3cd20d1b1d31e3c22e7c28871f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__i2c__macros__callback__events.html#gaa509ff3cd20d1b1d31e3c22e7c28871f">CY_SCB_I2C_SLAVE_WR_CMPLT_EVENT</a>&#160;&#160;&#160;(0x00000020UL)</td></tr>
<tr class="memdesc:gaa509ff3cd20d1b1d31e3c22e7c28871f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates the master completed writing to the slave (set by the master Stop or Restart) <br /></td></tr>
<tr class="separator:gaa509ff3cd20d1b1d31e3c22e7c28871f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga88e999437b51f24bdaf50c6dac83d81c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__i2c__macros__callback__events.html#ga88e999437b51f24bdaf50c6dac83d81c">CY_SCB_I2C_SLAVE_ERR_EVENT</a>&#160;&#160;&#160;(0x00000040UL)</td></tr>
<tr class="memdesc:ga88e999437b51f24bdaf50c6dac83d81c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates the I2C hardware detected an error.  <a href="#ga88e999437b51f24bdaf50c6dac83d81c">More...</a><br /></td></tr>
<tr class="separator:ga88e999437b51f24bdaf50c6dac83d81c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaea716088b093bc6decbdbcb775462466"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__i2c__macros__callback__events.html#gaea716088b093bc6decbdbcb775462466">CY_SCB_I2C_MASTER_WR_IN_FIFO_EVENT</a>&#160;&#160;&#160;(0x00010000UL)</td></tr>
<tr class="memdesc:gaea716088b093bc6decbdbcb775462466"><td class="mdescLeft">&#160;</td><td class="mdescRight">All data specified by <a class="el" href="group__group__scb__i2c__master__high__level__functions.html#ga91f7a32d2a20cf3deebe01cef8d9d000">Cy_SCB_I2C_MasterWrite</a> has been loaded into the TX FIFO.  <a href="#gaea716088b093bc6decbdbcb775462466">More...</a><br /></td></tr>
<tr class="separator:gaea716088b093bc6decbdbcb775462466"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf02c69c9cef5ecd87100df9d8ec9ea0f"><td class="memItemLeft" align="right" valign="top"><a id="gaf02c69c9cef5ecd87100df9d8ec9ea0f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__i2c__macros__callback__events.html#gaf02c69c9cef5ecd87100df9d8ec9ea0f">CY_SCB_I2C_MASTER_WR_CMPLT_EVENT</a>&#160;&#160;&#160;(0x00020000UL)</td></tr>
<tr class="memdesc:gaf02c69c9cef5ecd87100df9d8ec9ea0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">The master write started by <a class="el" href="group__group__scb__i2c__master__high__level__functions.html#ga91f7a32d2a20cf3deebe01cef8d9d000">Cy_SCB_I2C_MasterWrite</a> is complete. <br /></td></tr>
<tr class="separator:gaf02c69c9cef5ecd87100df9d8ec9ea0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga692e9cdd3ec1afa5950905558dc915d3"><td class="memItemLeft" align="right" valign="top"><a id="ga692e9cdd3ec1afa5950905558dc915d3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__i2c__macros__callback__events.html#ga692e9cdd3ec1afa5950905558dc915d3">CY_SCB_I2C_MASTER_RD_CMPLT_EVENT</a>&#160;&#160;&#160;(0x00040000UL)</td></tr>
<tr class="memdesc:ga692e9cdd3ec1afa5950905558dc915d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">The master read started by <a class="el" href="group__group__scb__i2c__master__high__level__functions.html#ga83185adeefa83640ac09852c9d6cf426">Cy_SCB_I2C_MasterRead</a> is complete. <br /></td></tr>
<tr class="separator:ga692e9cdd3ec1afa5950905558dc915d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad25268ddc924bd9ab5b72cbe4ddd9df8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__i2c__macros__callback__events.html#gad25268ddc924bd9ab5b72cbe4ddd9df8">CY_SCB_I2C_MASTER_ERR_EVENT</a>&#160;&#160;&#160;(0x00080000UL)</td></tr>
<tr class="memdesc:gad25268ddc924bd9ab5b72cbe4ddd9df8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates the I2C hardware has detected an error.  <a href="#gad25268ddc924bd9ab5b72cbe4ddd9df8">More...</a><br /></td></tr>
<tr class="separator:gad25268ddc924bd9ab5b72cbe4ddd9df8"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="gab1b3af0c61cd17e209d3c95aedd89f7b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab1b3af0c61cd17e209d3c95aedd89f7b">&#9670;&nbsp;</a></span>CY_SCB_I2C_SLAVE_READ_EVENT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_SCB_I2C_SLAVE_READ_EVENT&#160;&#160;&#160;(0x00000001UL)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Indicates that the slave was addressed and the master wants to read data. </p>
<p>This event can be used to configure the slave Read buffer. </p>

</div>
</div>
<a id="gacbc6de23c9ce6b3b01746244e27c8bed"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gacbc6de23c9ce6b3b01746244e27c8bed">&#9670;&nbsp;</a></span>CY_SCB_I2C_SLAVE_WRITE_EVENT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_SCB_I2C_SLAVE_WRITE_EVENT&#160;&#160;&#160;(0x00000002UL)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Indicates that the slave was addressed and the master wants to write data. </p>
<p>This event can be used to configure the slave Write buffer. </p>

</div>
</div>
<a id="gabe3e8539e5a47b1a419cd07a5aa1531e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabe3e8539e5a47b1a419cd07a5aa1531e">&#9670;&nbsp;</a></span>CY_SCB_I2C_SLAVE_RD_IN_FIFO_EVENT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_SCB_I2C_SLAVE_RD_IN_FIFO_EVENT&#160;&#160;&#160;(0x00000004UL)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>All slave data from the configured Read buffer has been loaded into the TX FIFO. </p>
<p>The content of the Read buffer can be modified. Applicable only if the TX FIFO is used. </p>

</div>
</div>
<a id="gada6c481df3423c3c0d7db05fd626534a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gada6c481df3423c3c0d7db05fd626534a">&#9670;&nbsp;</a></span>CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT&#160;&#160;&#160;(0x00000008UL)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The master has read all data out of the configured Read buffer. </p>
<p>This event can be used to configure the next Read buffer. If the buffer remains empty, the <a class="el" href="group__group__scb__i2c__macros.html#gad56a26de596ed39516b91adc50db4bf9">CY_SCB_I2C_DEFAULT_TX</a> bytes are returned to the master. </p>

</div>
</div>
<a id="ga88e999437b51f24bdaf50c6dac83d81c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga88e999437b51f24bdaf50c6dac83d81c">&#9670;&nbsp;</a></span>CY_SCB_I2C_SLAVE_ERR_EVENT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_SCB_I2C_SLAVE_ERR_EVENT&#160;&#160;&#160;(0x00000040UL)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Indicates the I2C hardware detected an error. </p>
<p>Check <a class="el" href="group__group__scb__i2c__slave__functions.html#gab3e1c474d6a5c7c5547ea08aa5d59e22">Cy_SCB_I2C_SlaveGetStatus</a> to determine the source of the error. </p>

</div>
</div>
<a id="gaea716088b093bc6decbdbcb775462466"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaea716088b093bc6decbdbcb775462466">&#9670;&nbsp;</a></span>CY_SCB_I2C_MASTER_WR_IN_FIFO_EVENT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_SCB_I2C_MASTER_WR_IN_FIFO_EVENT&#160;&#160;&#160;(0x00010000UL)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>All data specified by <a class="el" href="group__group__scb__i2c__master__high__level__functions.html#ga91f7a32d2a20cf3deebe01cef8d9d000">Cy_SCB_I2C_MasterWrite</a> has been loaded into the TX FIFO. </p>
<p>The content of the master write buffer can be modified. Applicable only if the TX FIFO is used. </p>

</div>
</div>
<a id="gad25268ddc924bd9ab5b72cbe4ddd9df8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad25268ddc924bd9ab5b72cbe4ddd9df8">&#9670;&nbsp;</a></span>CY_SCB_I2C_MASTER_ERR_EVENT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_SCB_I2C_MASTER_ERR_EVENT&#160;&#160;&#160;(0x00080000UL)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Indicates the I2C hardware has detected an error. </p>
<p>It occurs together with <a class="el" href="group__group__scb__i2c__macros__callback__events.html#ga692e9cdd3ec1afa5950905558dc915d3">CY_SCB_I2C_MASTER_RD_CMPLT_EVENT</a> or <a class="el" href="group__group__scb__i2c__macros__callback__events.html#gaf02c69c9cef5ecd87100df9d8ec9ea0f">CY_SCB_I2C_MASTER_WR_CMPLT_EVENT</a> depends on the direction of the transfer. Check <a class="el" href="group__group__scb__i2c__master__high__level__functions.html#ga652a3b9da6db2424fed62c28c6347ef3">Cy_SCB_I2C_MasterGetStatus</a> to determine the source of the error. </p>

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